Design Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Design Verification Engineer THE ROLE : As a Design Verification Engineer, you develop and maintain a functional coverage model using System Verilog - UVM test benches. Additionally, you will contribute to enhancing the verification strategy and architecture of IP testbenches, ensuring test bench scalability, quality, and meeting sign-off targets. You will actively interact with RTL and Verification team, providing constant feedback, support and hands on approach on quality improvements. THE PERSON : You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Perform pre-Silicon Verification of next generation high performance Microprocessor designs and related IPs. Create and execute on testbench specifications, coverage and verification testplans at unit level design. Implement constrained-random sequences, agents, and environments using the UVM methodology, to ensure design functionality according to specifications Develop, simulate and debug high level language testbench components including stimulus drivers, behavioral models, monitors and checkers in SystemVerilog. Run regressions and root-cause RTL / DV defects Collaborating directly with designers on new features bring up and debugging of existing designs QUALIFICATIONS : Experience with code and functional coverage collection / analysis Experience with verification methodologies such as UVM (Universal Verification Methodology) or other simulation-based verification techniques. Experience or familiarity with functional verification tools by VCS,Cadence,Mentor Graphics. Experience working in a Unix / Linux environment. Experience with scripting languages - Python, Perl, Shell scripting REQUIRED SKILLS : Good knowledge of English language. Exposure to OOP languages (C++ / System Verilog) Exposure to Digital Circuit Design (VHDL / Verilog) Good understanding of computer organization / architecture. Strong analytical, debug and problem-solving skills. Proactive with a consulting mindset, highly organized, continuous learner ACADEMIC CREDENTIALS : Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. #LI-PL1 #LI-HYBRID #Iasi Benefits offered are described : AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.Design Verification Engineer THE ROLE : As a Design Verification Engineer, you develop and maintain a functional coverage model using System Verilog - UVM test benches. Additionally, you will contribute to enhancing the verification strategy and architecture of IP testbenches, ensuring test bench scalability, quality, and meeting sign-off targets. You will actively interact with RTL and Verification team, providing constant feedback, support and hands on approach on quality improvements. THE PERSON : You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Perform pre-Silicon Verification of next generation high performance Microprocessor designs and related IPs. Create and execute on testbench specifications, coverage and verification testplans at unit level design. Implement constrained-random sequences, agents, and environments using the UVM methodology, to ensure design functionality according to specifications Develop, simulate and debug high level language testbench components including stimulus drivers, behavioral models, monitors and checkers in SystemVerilog. Run regressions and root-cause RTL / DV defects Collaborating directly with designers on new features bring up and debugging of existing designs QUALIFICATIONS : Experience with code and functional coverage collection / analysis Experience with verification methodologies such as UVM (Universal Verification Methodology) or other simulation-based verification techniques. Experience or familiarity with functional verification tools by VCS,Cadence,Mentor Graphics. Experience working in a Unix / Linux environment. Experience with scripting languages - Python, Perl, Shell scripting REQUIRED SKILLS : Good knowledge of English language. Exposure to OOP languages (C++ / System Verilog) Exposure to Digital Circuit Design (VHDL / Verilog) Good understanding of computer organization / architecture. Strong analytical, debug and problem-solving skills. Proactive with a consulting mindset, highly organized, continuous learner ACADEMIC CREDENTIALS : Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field. #LI-PL1 #LI-HYBRID #Iasi Benefits offered are described : AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and / or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.